1. Field of the Invention
The present invention relates generally to semiconductor devices and, more specifically to a semiconductor device module that includes a plurality of integrated circuit devices formed by wafer-scale integration and oriented in a stacked configuration upon a heat dissipating base plate; and high-speed axial optical interconnects used to provide interconnections between the integrated circuit devices located at each stack level.
2. Description of the Prior Art
Conventionally, the manufacture of integrated circuits is accomplished by simultaneously fabricating a plurality of identical circuits on a single wafer. The wafer is later scribed into a plurality of chips that are separately packaged and later integrated into a larger system. For example, spacecraft avionics systems are large integrated systems having circuits built from conventional electronic chips and components. The chips are produced and packaged by many different manufacturers and because the packaged chips are substantially larger than the chips themselves, the circuits are typically much larger than is necessary to perform each circuit""s intended function. These packaged chips may be placed into several spacecraft avionics units (black boxes) where each unit contains a specific function required for the given spacecraft system. More specifically, integrated circuits (ICs) on wafer board assemblies are enclosed inside black boxes where the circuitry contained within a particular black box communicates with other black boxes through limited bandwidth copper wires or optical fibers. As a result, connections between the black boxes are lossy and the number of spacecraft avionics units required for a particular system is typically large. The quantity, size, and interconnections required for such units necessitates spreading the units over a large physical area, thereby, preventing satellites or similar spacecraft from being compact and lightweight structures.
Wafer-scale integration has been described in the art as a method for alleviating individual chip packaging and integration by including all of the processing required for a particular function in a single integrated circuit formed on a single semi-conductor wafer. It has further been described as a means for meeting the demands of high-speed processing since, by including all of the processing means of a particular application in a single integrated circuit, short and high-speed interconnections may be formed. However, wafer-scale integration is not without its disadvantages, since defects due to the presence of impurities in the semiconductor crystal structure can occur and such defects can prevent individual circuit components located on the area of the defect from functioning properly. The larger the surface area of the wafer, the greater the number of defects; therefore, the ability to increase the wafer size to accommodate larger and larger systems is obviated in the absence of a defect-free wafer.
Various means of detecting and bypassing wafer defects have been utilized to mitigate the effects that such defects have on wafer-scale integrated circuits. Generally, the operative circuits or devices on a wafer are electrically isolated from the inoperative devices through the use of discretionary connections. For example, U.S. Pat. No. 5,514,884 discloses a method of using multiple identical blocks of addressable circuitry that are tested prior to interconnection to compensate for the defects in a wafer-size integrated circuit. The multiple identical blocks of circuit elements and multiple identical blocks of control logic are provided on a wafer where both the blocks of circuit elements and the blocks of control logic are small enough that blocks found to be defective can be discarded without significantly reducing the size of the device. U.S. Pat. No. 5,274,264 discloses a defect tolerant power distribution network for wafer-scale integrated circuits, and a method for detecting and removing short circuits from the network. Portions of the conductive lines in the power distribution network are fabricated with an area whose width is reduced relative to the remainder of the line. The amount of reduction in the line is sufficient to produce a hot spot in response to current flow to a short circuit that is located at an electrically downstream location on the line. Upon locating the hot spot as being associated with a specific circuit, the shorted circuit is removed from the remainder of the network by such means as laser cutting. U.S. Pat. Nos. 5,498,886 and 5,576,554 disclose forming a plurality of circuit modules on a wafer and grouping the modules into blocks arranged on a rectangular grid. An interconnect network including signal lines and power lines, each with built-in redundancy, surrounds each block. Each module and each segment of the interconnect network are tested and, by using fusible links, the defect-free segments of the interconnect network are connected to the functional circuit modules. U.S. Pat. No. 5,430,734 discloses an integrated circuit device that includes a wafer containing dynamically configurable gate arrays. The device provides a fault-tolerant design that addresses manufacturing defects by mapping all defective gate arrays and defective portions of each gate array on the wafer. Such defect mapping occurs during initial wafer testing following the wafer fabrication and the mapping information is later used to program the desired wafer functions to exclude defective portions of the wafer. U.S. Pat. No. 5,140,189 discloses creating externally formed connections to a wafer-scale semiconductor device to avoid wafer level defects located at various sites on the wafer. In particular, small external shorting blocks or patch circuits are utilized to define spare sites that may be used as replacement sites for defective primary sites. The patch circuit is used in combination with a decoder circuit that is coupled to a predetermined number of spare sites on a fully processed wafer-scale integrated (WSI) wafer. The decoder contains one enabling output for each spare site so that connections completed by the shorting block or patch circuit can assign a logical address for a defective primary site to a designated spare site. Control circuits also exist in the wafer to electrically remove one or more defective primary sites and to activate a required number of spare sites that operate as replacement sites for the defective primary sites. U.S. Pat. No. 5,084,838 discloses a plurality of integrated circuits mounted on a large-scale integrated circuit device that are each provided with a bypass circuit that selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, all unit integrated circuits that are judged to be normal among a plurality of unit integrated circuits disposed along one row are coupled together.
To avoid testing individual circuits and manually connecting circuits to bypass defective circuit components, U.S. Pat. No. 5,287,345 discloses an array of interconnected node units formed as an integrated circuit on a semiconductor wafer for use in data handling, data processing or data storage. Each node unit includes a controlled switch for routing signal packets to destination node units whose addresses are included in the packets and also includes an automatic self-test function that, following satisfactory completion of the self-test, transmits a signal to adjacent node units that it is functioning properly. The controller of a node unit switch stores datum concerning which adjacent node units are defective and directs signal packets on paths around the defective node units.
Notwithstanding that wafer defect avoidance techniques, like those previously described, may be necessary to produce operative wafer-scale integrated circuits, such techniques may not, by themselves, be acceptable for wafer-scale integration that meets the demands of applications requiring increased processing speed and performance, as well as increased integration density of microelectronic components. Such applications, for example in avionics systems and other similarly larger and complex systems, could potentially require considerably large wafers. And, as previously described, increases in wafer size (or wafer surface area) are accompanied by proportional increases in the number of wafer defects. The more redundancy one employs to overcome wafer defects and increase yield, the more system performance is sacrificed. As a result, practical limitations on the wafer size and the circuit density may be necessary to avoid sacrificing system performance.
However, one method that has been described in the art for creating higher density circuits includes interconnecting individual integrated circuit wafers in a stacked wafer structure. Several approaches have been used to interconnect the wafers in the stack. In some approaches, the wafers in the stack are electrically interconnected using solid vertical columns of metallic conductive feed-throughs, such as copper. However, the use of solid feed-throughs to interconnect wafers may cause damage to the stacked wafer structure because of incompatible coefficients of thermal expansion between the feed-through materials and the integrated circuit wafer materials. Other approaches, like the approach disclosed in U.S. Pat. No. 5,229,647, provide each wafer in the stack with through holes that expose bonding pads on the wafers. The bonding pads of the wafers in the stack are then electrically connected by either filling the through holes with electrically conductive liquid bumps, or inserting some suitable electrically conductive material into the through holes to provide a continuous vertical electrical connection between the wafers. A disadvantage of such approaches includes the need for special tooling to create the electrically conductive bumps at predetermined uniform heights. Still other approaches, for example U.S. Pat. No. 5,661,087, include providing electrical interconnections to points along the periphery of stacked wafer segments. These approaches are subject to disadvantages similar to those observed in the bonding pad approaches described above, namely, they require a special dispensing mechanism to dispense the conductive traces (e.g. silver-filled epoxy) along the periphery of the wafer segments. Moreover, the problem with the stacked wafer approaches discussed above and similar approaches is the wafers in the stack are electrically interconnected. Because of recent advances in semiconductor device fabrication and high-speed processing requirements, an integrated optics approach to signal transmission and processing offers significant advantages both in performance and cost when compared to conventional electrical methods.
What is needed, therefore, is a semiconductor device module that includes a plurality of stacked integrated circuit devices formed by wafer-scale integration, with high-speed axial optical interconnects used to provide interconnections between the integrated circuit devices located at each stack level thereby enabling the functions of large-scale systems to be distributed among multiple such wafer-scale devices with a result that is physically equivalent to all of the system circuitry being monolithically integrated on one very large wafer. Moreover, since using WSI technology alone is not sufficient to accomplish a spacecraft system, or a similarly large and complex system, due to heat dissipation requirements (usually greater than 7,000 Watts), the semiconductor device module of the present invention provides the capability to dissipate significant amounts of heat in a very compact area.
The preceding and other shortcomings of the prior art are addressed and overcome by the present invention that provides a wafer-scale module. The module includes a plurality of wafers, each having a semiconductor layer formed thereon, a plurality of through holes arranged circumferentially thereon and extending normal to a plane thereof, a plurality of optical transmission interfaces extending normal to the wafer plane, and a plurality of integrated circuits formed on the semiconductor wafer. The plurality of integrated circuits include a plurality of nodes, each node being coplanar with the wafer and proximate to one optical transmission interface. Each node also has the capability for transmitting and receiving optical data to and from the plurality of integrated circuits. The module also includes a plurality of optical waveguides, each extending normal to a plane of each wafer located in the stack and axially through one respective optical transmission interface at each wafer level in the stack. A top plate is disposed on the plurality of stacked wafers and includes a plurality of through holes arranged circumferentially thereon extending normal to a plane of the wafer. Each top plate through hole has corresponding alignment to one wafer through hole. A base plate is disposed opposite the top plate such that the plurality of stacked wafers are sandwiched between the top plate and the base plate. The base plate provides thermal dissipation for the module and also includes a plurality of through holes arranged circumferentially thereon and extending normal to a plane thereof. Each base plate through hole having corresponding alignment to one top plate through hole and one wafer through hole so that the module can be fastened together via the base plate, top plate and stacked wafer through holes.